Decoding method and apparatus for cyclic codes

ABSTRACT

In an apparatus for decoding cyclic codes generated by a generator polynomial ##EQU1## (where P i  (x) is a m i  -order irreducible polynomial) including 0-th to l-th feedback shift registers corresponding to the terms (x c  +1) and P i  (x), a coincidence circuit for detecting coincidence of a predetermined number of low order bits of said 0-th to l-th feedback shift registers and all-zero conditions of a high order bits, the predetermined number being a minimum one of numbers of bits (c, m 1 , m 2 , . . . m l ) of the feedback shift register, the 0-th feedback shift register having an output terminal thereof connected to an input terminal thereof, and the 1st to l-th feedback shift registers each having an output terminal thereof connected to an input terminal thereof and having exclusive OR gates inserted between stages determined by the associated simple polynomial, exclusive OR gates each receiving the output of the associated feedback shift register as one input thereto; a method for decoding the cyclic code for correcting a burst error by shifting the 0-th to l-th feedback shift registers until the coincidence circuit detects the coincidence, comprising the steps of; shifting at least one of said 0-th to l-th feedback shift registers a predetermined number of times; and simultaneously shifting the 0-th to l-th feedback shift registers after the predetermined number of shifting until the coincidence circuit detects the coincidence.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to method and apparatus for decoding acyclic code.

2. Description of the Prior Art

A cyclic code is one of the codes for correcting a burst error (having aburst length b) generated in a data transmission line.

A generator polynomial of the cyclic code is expressed by ##EQU2## whereP_(i) (x) is a m_(i) -order irreducible polynomial. The irreduciblepolynomial is defined as one which is not divisible without a residue byany polynomial having an order of no less than one and no more thanm_(i) -1. Hereinafter, ##EQU3##

When the number of bits of the data is s and n-m-c≧s (where n is a codelength of the cyclic code) and c≧2b+d-1, any burst error which meets b≦mcan be corrected. (See "Burst-Correcting Codes with High Speed Decoding"by Robert T. Chien, IEEE Trans. on Information Theory, Vol. IT-15, No.1, January 1969.)

The code length n of the cyclic code is a least common multiple of aperiod e_(i) of P_(i) (x) and c, that is, LCM (c, e₁, e₂, . . . e_(l)).

The period e_(i) of P_(i) (x) is the order of a minimum order polynomial(1+x^(e).sbsp.i) of polynomials which have forms of (1+x.sup.α) and aredivisible by P(x) without a residue.

At first an encoding method of the cyclic code is described.

I. Encoding Method of the Cyclic Code

Data D(x) to be transmitted is expressed as

    D(i x)=a.sub.s-1 ·x.sup.s-1 +a.sub.s-2 ·x.sup.s-2 + . . . +a.sub.o                                                  ( 2)

The cyclic code is encoded by expressing a product D(x)·x^(m+c) suchthat it is divisible by a generator polynomial G(x) without a residue.The polynomial D(x) represents data (a_(s-1), a_(s-2), . . . a_(o)) sentout to the transmission line.

A residue produced when D(x)·x^(m+c) is divided by G(x) is representedby a check pattern R(x)=R_(m+c-1) ·x^(m+c-1) +R_(m+c-2) ·x^(m+c-2) + . .. +R_(o) (a bit length of the check pattern R(x) is m+c). Thus,

    D(x)·x.sup.m+c =G(x)·Q(x)+R(x)

where Q(x) is a quotient.

A code word F(x) of the cyclic code is represented by

    F(x)=D(x)·x.sup.m+c +R(x)                         (3)

F(x) is divisible by G(x) without a residue and the encoding of thecyclic code is terminated.

A divider for dividing D(x)·x^(m+c) by G(x) and producing the residueR(x) may be a conventional one.

II. Method of Decoding the Cyclic Code

A receiving station receives a code word F*(x). F*(x) is divided by thegenerator polynomial. It must be divisible without a residue if no erroris included in F*(x). (The transmitted code word F(x) is divisible byG(x) without a residue.) However, if F*(x) includes a burst error B(x)starting from a (j+1)th bit, F*(x) is not divisible by G(x). F*(x) underthis condition is represented by

    F*(x)=F(x)+x.sup.j ·B(x)                          (4)

The generator polynomial G(x) consists of the polynomial (x^(c) +1) andthe irreducible polynomial P_(i) (x). Residues produced by dividingF*(x) by those polynomials are syndromes R_(c) (x) and RPi(x),respectively. Those syndromes are multiplied by x^(n-j) and the productsare divided by (x^(c) +1) and P_(i) (x), respectively. If residues areequal, (j+1) represents the error position and x^(n-j) ·RPi(x)represents the burst error B(x). Accordingly, the followings are met.##EQU4## Both sides are multiplied by x^(n-j) and the equations arerewritten as follows. ##EQU5## where x^(j) ·B(x)≡R_(c) (x) (mod P(x))represents that the residues when divided by P(x) are equal.

Hereinafter, the following generator polynomial G(x) of the cyclic codeis assumed.

    G(x)=(x.sup.22 +1)·(x.sup.12 +x.sup.11 +x.sup.10 + . . . +x+1)·(x.sup.11 +x.sup.7 +x.sup.6 +x+1)·(x.sup.11 +x.sup.9 +x.sup.7 +x.sup.6 +x.sup.5 +x+1)                 (7)

    P.sub.1 (x)=x.sup.12 +x.sup.11 +x.sup.10 + . . . +x+1

    P.sub.2 (x)=x.sup.11 +x.sup.7 +x.sup.6 +x+1

    P.sub.3 (x)=x.sup.11 +x.sup.9 +x.sup.7 +x.sup.6 +x.sup.5 +x+1

In the polynomial (7), (x¹² +x¹¹ +x¹⁰ + . . . +x+1) divides (x¹³ +1) andhence a period of P_(i) (x) is 13. Periods of the polynomials (x¹¹ +x⁷+x⁶ +x+1) and (x¹¹ +x⁹ +x⁷ +x⁶ +x⁵ +x+1) and 89 and 23, respectively.(See "Code Theory" by H. Miyagawa, Y. Iwadare and H. Imai, edited byShokodo, page 530). Accordingly, the code length n is LCM (22, 13, 89,23)=585442, where LCM is a least common multiple. Thus, a single bursterror up to 11 bits can be corrected.

FIG. 1 shows a decoder. FSRC denotes a divider which divides the inputcode F*(x) supplied via a signal line 160 by (x^(c) +1). FSRP₁, FSRP₂and FSRP₃ denote dividers which divide the input code F*(x) by thepolynomials P₁ (x), P₂ (x) and P₃ (x), respectively. Details thereofwill be explained in embodiments of the invention. A coincidence circuit223 checks bit-by-bit coincidence of low order 11 bits of the FSRC andlow order 11 bits of the FSRP₁. Coincidence circuits 324 and 325 checkbit-by-bit coincidence of the low order 11 bits of the FSRP₁ and the loworder 11 bits of the FSRP₂, and the bits of the FSRP₂ and the bits ofthe FSRP₃, respectively. A zero detector 326 checks if all of high order11 bits of the FSRC and high order one bit of the FSRP₁ are zero. Whenthe low order 11 bits of the FSRC, the low order 11 bits of theFSRP.sub. 1, the bits of the FSRP₂ and the bits of the FSRP₃ havebit-by-bit correspondence and the high order 11 bits of the FSRC and thehigh order one bit of the FSRP₁ are zero, a signal line 171 connected toan output of an AND gate 170 is rendered high level.

When the input code F*(x) has been inputted to the FSRC, FSRP₁, FSRP₂and FSRP₃, syndromes S_(c) (x), S_(p1) (x), S_(p2) (x) and S_(p3) (x)therefor meet the following relationships because the input code isinputted to an m'-th stage of respective shift registers (m'=min (m₁,m₂, m₃)). ##EQU6## By multiplying both sides of the equations (8) byx^(n-j-m'), the left sides become B(x). It represents that all low orderm' bits of the FSRC, FSRP₁, FSRP₂ and FSRP₃ are coincident and all bitsin higher orders than m' are zero. B(x) represents the error pattern andj represent an error location.

In this prior art decoding method, a maximum of (n-m') times of shiftingare necessary to find j.

When such a cyclic code is actually used, a maximum of (n-m') times ofshifting are required whatever low the order of the input code F*(x) is.

For example, in a disk data, one sector has 128 bytes (1024 bits) or 256bytes (2047 bits). On the other hand, in a fire code which uses thegenerator polynomial G(x) as represented by the formula (7), n=585442which is approximately 200-500 times as long. Even in this case,approximately 580 thousands times of shifting are required.

In order to reduce the number of times of shifting, it has been proposedto use the "Chinese Remainder Theorem" (See "Burst-Correcting Codes withHigh Speed Decoding" referenced above.) However, this method requires aninteger divider having a divisor n and hence a complex hardware.

SUMMARY OF THE INVENTION

It is an object of the present invention to provde a method andapparatus for decoding a cyclic code with a reduced number of times ofshifting and small increase of hardware, for an input code having ashort code length.

In describing the present invention, let us assume that the input codeF*(x) is represented as follows.

    F*(x)=b.sub.s+m+c-1 ·x.sup.s+m+c-1 +b.sub.x+m+c-2 ·x.sup.s+m+c-2 + . . . +b.sub.o                  ( 9)

where s is the length of the data field of the input code and n>>x+m+c,and b_(s+m+c-1) ˜b_(o) are input data bits.

The code length of the Cyclic code F(x) is n. Accordingly, coefficientsof terms x^(n-1) to x^(s+m+c) in the formula (9) are zero.

In order to detect the burst error from the input code F*(x), at least(n-s-m-c) times of shifting by the formula (8) are required. Sincen>>s+m+c, the number of times of shifting is very large. In other words,the error location j cannot be detected before such number of times ofshifting. If most parts of the huge number of times of shifting can beomitted, the object of the present invention can be attained.

In the present invention, the following points were noticed.

I. The irreducible polynomial P_(i) (x) has a period e_(i). It meansthat if a product of a polynomial R_(pi) (x) having a lower order thanP_(i) (x) and x^(ei) is divided by P_(i) (x), a residue is equal to thepolynomial R_(pi) (x). For example, in FIG. 1, if the input signal 160is all-zero, a content of the divider FSRP₁ returns to the original oneafter e₁ times of shifting.

II. When the code word F(x) of a cylic code is divided into e_(i) -bitblocks (where i is an arbitrary number), the input code word F*(x)appears in the latter half blocks.

III. The polynomial (x^(c) +1) also has a period c. For example, if theinput signal 160 is all-zero, the content of the divider FSRC of FIG. 1returns to the original one after c times of shifting.

IV. The polynomial P_(i) (x) and the polynomial (x^(c) +1) havedifferent periods from each other. When the polynomials R_(p1) (x), . .. , R_(pl) (x), R_(c) (x) are multiplied by x^(ei') and the products aredivided by P₁ (x), . . . , P_(l) (x), (x^(c) +1), respectively,

    x.sup.ei' ·R.sub.pi (x)≡R.sub.pi (x) (mod P.sub.i (x)) when i=i'

    x.sup.ei' ·R.sub.pi (x)≡x.sup.ei'-βiei ·R.sub.pi (x) (mod P.sub.i (x)) when i=i'

    x.sup.ei' ·R.sub.c (x)≡x.sup.ei'-βcC ·R.sub.c (x) (mod x.sup.c +1) for polynomial (x.sup.c +1)

where β_(i) is a largest integer which satisfies e_(i) '≧β_(i) e_(i),and β_(c) is a largest integer which satisfies e_(i) '≧β_(c) C.

The integers βi and β_(c) can be obtained by calculation. Then, (e_(i)'-β_(i) e_(i)) and (e_(i) '-β_(c) C) are obtained, and x^(ei'-)βiei·R_(pi) (x) is divided by P_(i) (x) and x^(ei'-)βcC ·R_(c) (x) isdivided by (x^(c) +1). This is equivalent to multiplying R_(pi) (x) andR_(c) (x) by e_(i) ', respectively and then dividing products obtainedby the multiplication by P_(i) (x) and (x^(c) +1), respectively.

V. The order (s+m+c) of the input code F*(x) is much smaller than thecode length n.

In the prior art decoding method, at least (n-s-m-c) times of divisionare required before the error location is detected. The periods e_(i)and c are cycled t_(i) and t_(c) times (i=1-l) respectively, during thisperiod. The values of t_(i) and t_(c) can be obtained by calculation. Onthe other hand,

    x.sup.ei'·ti' ·R.sub.pi (x)≡R.sub.pi (x) (mod P.sub.i (x)) for i=i'

    x.sup.ei'·ti' ·R.sub.pi (x)≡x.sup.pi ·R.sub.pi (x) (mod P.sub.i (x)) for i≠i'

    x.sup.ei'·ti ·R.sub.c (x)≡x.sup.pc ·R.sub.c (x) (mod x.sup.c +1) for polynomial (x.sup.c +1)

The periods e_(i) and c are cycled k_(i) and k_(c) times, respectively,during (e_(i) '·t_(i) ') cycles. The difference between e_(i) '·t_(i) 'and e_(i) ·k_(i) is P_(i), and the difference between e_(i) '·t_(i) 'and c·k_(c) is P_(c). For i=i', it may be regarded that P_(i) =0. P_(i)and P_(c) can be obtained by calculation. Thus, if P_(i) and P_(c) arecalculated, R_(pi) (x) is multiplied by x^(pi), R_(c) (x) is multipliedby x^(pc) and the products are divided by P_(i) (x) and (x^(c) +1),respectively, it is equivalent to multiplying R_(pi) (x) and R_(c) (x)by x^(ei')·ti', respectively, and dividing the products by P_(i) (x) and(x^(c) +1), respectively.

VI. Those are sequentially multiplied by x and the products are dividedby P_(i) (x) and (x^(c) +1), respectively. The error location isdetected by the number i^(j) of multiplication by x when the residues ofboth divisions are equal.

The above operations will be represented by formulas.

The syndromes R_(pi) (x) and R_(c) (x) are first determined. ##EQU7##Then, R_(pi) (x) and R_(c) (x) are multiplied by x^(pi) and x^(pc),respectively, and the products are divided by P_(i) (x) and (x^(c) +1),respectively. For i=i', P_(i) =0. ##EQU8## Finally, those are multipliedby x^(j), respectively. ##EQU9## The j when all of B_(p1) (x)˜B_(pl) (x)and B_(c) (x) are equal represents the error location. The B_(p1) (x) atthis time represents the burst error B(x) pattern.

As described above, in the cyclic code which uses the generatorpolynominal G(x) shown in the formula (7), the code length n is 585442and approximately 580 thousands times of shifting are required to detectthe error. On the other hand, the number of bits of the disk data is1024 or 2048 bits. When the number s of data bits are much smaller thanthe code length n, the order (s+m+c) of the input code F*(x) representedby the formula (9) is much smaller than n and the terms x^(n-1) tox^(s+m+c) of the code word F(x) of the cyclic code are zero. In thepresent invention, when the order of the input code F*(x) is smallerthan the code length n of the cyclic code, for most parts of the codeword F(x) of the cyclic code which lack the initial input code wordF*(x), the results of shifting by the dividers if the shifting were madefor the above parts are set by a smaller number of times of preshiftingdetermined by calculation. Then, for the position which includes theinput code F*(x), the error location is detected by the cyclic codesystem.

The irreducible polynomial P_(i) (x) and the polynomial (x^(c) +1) haverespective periods, and the syndromes for those polynomials set in thedividers when the input code is received return to their originalcontents after the numbers of times of shifting corresponding to theperiods of the respective polynomials, if the input code is all-zero.Accordingly, the code word F(x) of the cyclic code is divided into thenumber of blocks equal to the number of bits of the period e_(n) of thepolynomial P_(n) (x), and for those blocks from the beginning of thecode word F(x) of the cyclic code to the block immediately before theblock which includes the highest order code of the input code F*(x)(hereinafter referred to a block containing no input code F*(x)), thecontent of the divider for the polynomial P_(n) (x) is not changedbecause it has shifted by an integer multiple of the period. For theother dividers, if they shift by maximum integer multiples of theperiods of the corresponding polynomials included in the blocks which donot include the input code word F*(x), the contents of the dividersreturn to the original ones, respectively. Thus, by shifting the dividerby the number of code bits remaining in the block, the result after theshifting of the above parts is obtained. In this manner, for the blockswhich do not contain the input code word F*(x), the shift results by thedividers are obtained by the small number of times of preshiftingdetermined by the calculation.

Accordingly, in accordance with the present invention, when the order ofthe input code word F*(x) is smaller than the code length n of thecyclic code, the number of times of shifting can be reduced to shortenthe decoding time. Portions of the code words of the cyclic code whichinclude the input code word F*(x) are decoded by the cyclic code systemwithout using complex hardware as required in a high speed decodingmethod. Thus, in accordance with the present invention, the high speeddecoding is attained without complex hardware. It is realized by addinga small amount of hardware for controlling preshifting.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a decoding circuit for a cyclic code used in the presentinvention,

FIG. 2 shows a control circuit in one embodiment of the presentinvention,

FIGS. 3 and 4 show timing charts for the circuit of FIG. 2,

FIG. 5 illustrates calculation,

FIG. 6 shows a timing chart fot the circuit of FIG. 2,

FIG. 7 shows an encoding circuit for a Fire code,

FIG. 8 shows a decoding circuit for the Fire code,

FIG. 9 shows a format of the Fire code,

FIG. 10 shows a control circuit,

FIGS. 11 and 12 show timing charts,

FIG. 13 illustrates calculation,

FIG. 14 shows a timing chart, and

FIG. 15 illustrates calculation.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

One embodiment of the present invention will now be explained byreferring to the drawings. Let us assume that the cyclic code which usesthe generator polynomial G(x) as represented by the formula (7). Asdescribed above, the periods of the polynomials (x²² +1), (¹² +x¹¹+x¹⁰ + . . . +x+1) are 22, 13, 89 and 23, respectively. Accordingly, thecode length n is given by

    n=LCM(22, 13, 89, 23)=22×13×89×23=585442

The length of the check pattern R(x) is 32 bits. One burst error up to11 bits is correctable.

FIGS. 1 and 2 show a decoder for the cyclic code represented by theformula (7) and a control circuit therefor. Stages 101-122 and anexclusive OR gate 301 constitute the divider FSRC having the polynomial(x²² +1) as a divisor. Stages 123-134 and exclusive OR gates 302-313constitute the divider FSRP₁ having the polynomial (x¹² +x¹¹ +x¹⁰ + . .. +x+1) as a divisor. Stages 135-145 and exclusive OR gates 314-316constitute the divider FSRP₂ having the polynomial (x¹¹ x⁷ +x⁶ +x+1) asa divisor. Stages 146-156 and exclusive OR gates 137-322 constitute thedivider FSRP₃ having the polynomial (x¹¹ +x⁹ +x⁷ +x⁶ +x⁵ +x+1) as adivisor.

The coincidence circuit 323 checks the coincidence between the low order11 bits of the FSRC and those of the FSRP₁, that is, the stages 101 and123, 102 and 124, 103 and 125, 104 and 126, 105 and 127, 106 and 128,107 and 129, 108 and 130, 109 and 131, 110 and 132, and 111 and 133. Thecoincidence circuit 324 checks the coincidence between the low order 11bits of the FSRP₁ and those of the FSRP₂, that is, the stages 123 and135, 124 and 136, 125 and 137, 126 and 138, 127 and 139, 128 and 140,129 and 141, 130 and 142, 131 and 143, 132 and 144, and 133 and 145. Thecoincidence circuit 325 checks the coincidence circuit 325 checks thecoincidence between the stages of the FSRP₂ and the FSRP₃, that is, thestages 135 and 146, 136 and 147, 137 and 148, 138 and 149, 139 and 150,140 and 151, 141 and 152, 142 and 153, 143 and 154, 144 and 155, and 145and 156. The zero detector 326 checks if all of the stages 112-122 and134 are zero. An AND gate 170 produces a high level output on a signalline 171 when all of the outputs of the coincidence circuits 323-325 andthe zero detector 326 are high level. Namely, the signal line 171 isasserted when all of the low order 11 bits of the FSRC, the low order 11bits of the FSRP₁, the bits of the FSRP₂ and the bits of the FSRP₃ arecoincident, and all of the high order 11 bits of the FSRC and the highorder one bit of the FSRP₁ are zero.

When the signal line 161 is high, the shifting by the FSRC is effected,and when the signal line 162, 163 or 164 are high, the shifting by theFSRP₁, FSRP₂ or FSRP₃ is effected.

The decoding operation is now explained. The decoding is done by thefollowing three steps.

(S1) Generation of syndromes S_(c) (x), S_(p1) (x), S_(p2) (x) andS_(p3) (x)

(S2) Preshifting of FSRC, FSRP₁, FSRP₂ and FSRP₃

(S3) Determination of error pattern B(x) and error location j

A circuit shown in FIG. 2 controls the above three steps, and FIGS. 3, 4and 5 show timing charts for the processes in the steps (S1), (S2) and(S3), respectively. The processes in the steps (S1), (S2) and (S3) willnow be explained.

The step (S1)-generation of syndromes is first explained. In FIG. 1, theinput data 160 is supplied to the FSRC, FSRP₁, FSRP₂ and FSRP₃ throughthe exclusive OR gates 301, 313, 316 and 322, respectively. A set of thecontents of the FSRC, FSRP₁, FSRP₂ and FSRP₃ at the end of the inputtingof the data is the syndrome to the cyclic code.

Shift enable signals 161-164 are generated by the circuit of FIG. 2 anda timing thereof is shown in the timing chart of FIG. 3. Referring toFIGS. 2 and 3, a signal line 200 from a transmission control unit 223for controlling the signal reception is rendered high level insynchronism with a clock φ₂ at a timing T₁ one clock before the firstbit data of the input data 160 (F*(x)) is supplied to the decoder. Thesignal line 200 sets the Q-output of a flip-flop 202 to the low level,and the Q-output is sent to signal lines 161-164 through a clock gate203 which receives a clock input φ₂ and OR gates 405-408. Accordingly,the signal lines 161-164 are rendered high level in synchronism with thefirst bit data of the input data 160. A signal line 201 indicates theend of the input data. It is rendered high level at a timing T₂ insynchronism with the last bit data of the input data. The signal line201 renders the Q-output of the flip-flop 202 high level and renders thesignal lines 161-164 low level through the clocked gate 203 and the ORgates 405-408. As shown in FIG. 3, when the syndromes S_(c) (x), S_(p1)(x), S_(p2) (x) and S_(p3) (x) are generated, the signal lines 161-164are rendered high level only for the period of data input. The set ofcontents of the dividers FSRC, FSRP₁, FSRP₂ and FSRP₃ at the end ofinputting of the last bit of the input data is the syndrome. In FIGS. 2,3, 4 and 6, φ₁ and φ₂ represent non-overlapping two-phase clocks.

The step (S2)-preshifting will now be explained. In this step, shiftingsare effected in the FSRC, FSRP₁, FSRP₂ and FSRP₃ by μ_(c), μ₁, μ₂ and μ₃times, respectively. Calculation method for μ_(c), μ₁, μ₂ and μ₃ will beexplained later. The preshifting serves to substantially reduce thenumber of times of shifting when the length of the input code F*(x) isshort, such as the disk data.

In FIG. 2, preshift select signals 409-412 from a shift controller 224which controls the shifting of the dividers are supplied to AND gates401-404. When the preshift select signals 409-412 are high level, anoutput of a clocked gate 208 is transmitted to the signal lines 161-164through the respective OR gates 405-408. The operation for preshiftingthe FSRC by μ_(c) times will be explained first. The preshift selectsignal 409 is high level and the preshift select signals 410-412 are lowlevel.

A preshift start signal 206 renders the Q-output of the flip-flop 207low level at a timing Ta (FIG. 4), and it is transmitted to the clockedgate 208 which receives the clock input φ₂, the AND gates 401-404 andthe OR gate 209. Thus, the signal lines 161 and 210 are rendered highlevel. The high level on the signal line 161 permits the shifting of theFSRC, and the high level on the signal line 210 permits the incrementingof the counter 213. The preshift start signal 206 is supplied to a clearterminal of a counter 213 through a NOR gate 211 and a clocked gate 212which receives a clock input φ₁. As a result, an output 214 from thecounter 213 is set to "0" in synchronism with the clock signal followingthe preshift start signal 206. A record length RL and a calculatednumber μ_(i) of times of preshifting are supplied to a preshift countdectector 215, which sets the signal line 216 at high level and resetsthe flip-flop 207 when the output of the clocked gate 208 is high leveland the output 214 of the counter 213 is (μ_(c) -1) (at a timing Tb). Asshown in FIG. 4, the signal line 161 is set to the high level only forthe durations of the μ _(c) clocks so that the shifting is effectedμ_(c) times in the FSRC. The preshiftings in the FSRP₁, FSRP₂ and FSRP₃are effected in the same manner as the preshifting in the FSRC. Of thepreshift select signals 409-412, only the signal 410, 411 or 412 isrendered high level, and the signal line 216 is rendered high level toreset the flip-flop 207 when the preshift count detector 215 detects (μ₁-1), (μ₂ -1) or (μ₃ -1). When the preshift count is zero, preshiftingneed not be effected.

The numbers μ_(c), μ₁, μ₂ and μ₃ of times of preshifting are explainedbelow. In the formula (7), the periods of the polynomials (x²² +1), (x¹²+x¹¹ +x¹⁰ + . . . +x+1), (x¹¹ +x⁷ +x⁶ +x+1) and (x¹¹ +x⁹ +x⁷ +x⁶ +x⁵+x+1) are 22, 13, 89 and 23, respectively, as described above.Accordingly, the patterns of the FSRC, FSRP₁, FSRP₂ and FSRP₃ return tothe original ones after 22, 13, 89 and 23 times of shifting,respectively. Accordingly, if the shifting is omitted by a number oftimes equal to a multiple of 89, no preshifting is required for theFSRP₂ and the preshiftings are required for the FSRC, FSRP₁ and FSRP₃,21, 12 and 22 times at maximum in accordance with the number of times ofshifting omitted. The numbers of times of preshifting are μ_(c), μ₁ andat this time it is possible to regard that μ ₃ and μ₂ is zero.

The μ_(c), μ₁ and μ₃ are formulated under the condition of nopreshifting in the FSRP₂, that is, μ₂ =0, a (RL×8+56)-bit data includinga 56-bit cyclic code check pattern R(x) is recorded on the disk, whereRL is the number of bytes of the record of the disk data. Accordingly,the length S of the input code word F*(x) is RL×8+56 and a maximum of585442-(RL×8+56) times of shifting can be omitted. If ##EQU10## ofleading bits are all-zero, the numbers μ_(c), μ₁ and μ₃ of times ofpreshift in the FSRC, FSRP₁ and FSRP₃ are represented by ##EQU11##

FIG. 5 shows examples of calculation of RL, μ_(c), μ₁ and μ₃, where [a]indicates a round-up number of a.

For the cyclic code having the generator polynomial shown in the formula(1), the numbers of times of preshifting when no shifting is effected inthe FSRP_(i) ' are represented by ##EQU12##

The final step (S3) will now be explained. This step determines theerror pattern B(x) and the error location j. In FIG. 2, the errordetection start signal 217 renders the Q-output of the flip-flop 218 lowlevel at a timing t₁ (FIG. 6) and renders the signal lines 161-164 highlevel through the clocked gate 219 which receives the clock input φ₂ andthe OR gates 405-408 and 209. At the same time, the error detectionstart signal 217 clears the counter 213 through the NOR gate 211 and theclocked gate 212. As shown in FIG. 6, the signal lines 161-164 arerendered high level at the clock φ₂ following to the error detectionstart signal 217 to start the shiftings in the FSRC, FSRP₁, FSRP₂ andFSRP₃, and the output 214 of the counter 213 is incremented from "0".

The shiftings in the FSRC, FSRP₁, FSRP₂ and FSRP₃ are effected until anyof the following conditions is met.

(C1) The low order 11 bits of the FSRC, the low order 11 bits of theFSRP₁, the bits of the FSRP₂ and the bits of the FSRP₃ are coincident,and the high order 11 bits of the FSRC and the high order one bit of theFSRP₁ are all-zero.

(C2) The number of times of shifting exceeds a predetermined number Q.

When the condition (C1) is met, the signal line 171 in FIG. 1 isasserted, and the error pattern is represented by the low order 11 bitsof the FSRC and the error location is at ##EQU13## from the leadingposition. The condition (C2) is detected by a shift over detector 220 ofFIG. 2 by the output of the clocked gate 219 and the counter output 214.The number Q may be a number larger than RL×8+56. The condition (C2)indicates the occurrence of a uncorrectable error.

When the condition (C1) or (C2) is detected, the signal line 222 in FIG.2 is rendered high level through the OR gate 221 and the flip-flop 218is reset at a timing t₂ (FIG. 6). As shown in FIG. 6, when the errordetection start signal 217 is rendered high level, the signal lines161-164 are rendered high level at the next clock φ₂ and the counteroutput 214 is incremented from "0". When the condition (C1) or (C2) isthereafter detected, the signal line 222 is rendered high level and thesignal lines 161-164 are negated. The incrementing of the counter isstopped.

The steps (S1), (S2) and (S3) described above are the decoding methodfor the cyclic code in the present invention.

Assuming that the cyclic code uses the generator polynomial representedby the formula (7) and the record length RL is 1024 bytes, the prior artmethod required a maximum of (585442-11) times of shifting while thepresent method requires only 8277+17+4+3=8301 times of shifting.Assuming that one shift cycle requires 100 ns (10 MHz), the prior artmethod needs approximately 59.5 seconds while the present method needsonly 0.8 second. An advantage from a practical use is great.

When the high speed decoding method based on the Chinese RemainderTheorem is used, even a 16-bit microcomputer is not appropriate becausemultiplication/division of integers of [log₂ 585442]=20 digits isrequired. The present method does not need such multiplication/division.

A second embodiment of the present invention in which the number ofirreducible polynomials in the generator polynomial of the cyclic codeis one is explained below.

The Fire code is one of the codes which correct the burst error (havinga length b) occurring in the data transmission line. (See "Code Theory"referenced above, page 309.)

The generator polynomial of the Fire code is represented by

    G(x)=P(x)(x.sup.c +1)                                      (11)

where P(x) is the irreducible polynomial. The irreducible polynomial oforder m is defined as one which is not divisible without a residue byany polynomial having an order no less than one and no more than m-1.

When the number of bits (code length) of the data is s and n-m-c≧s(where n is a code length of the Fire code) and c≧2b-1, all burst errorswhich meet b≦m can be corrected.

The code length n of the Fire code is a least common multiple of aperiod e of P(x) and c.

The period e of P(x) is the order of a minimum order polynomial(1+x^(e)) of polynomials which have forms of (1+x.sup.α) and aredivisible by P(x) without a residue.

An encoding method of the Fire code is first described.

(1) Encoding method of the Fire code

Data D(x) to be transmitted is expressed as

    D(x)=a.sub.s-1 ·x.sup.s-1 +a.sub.s-2 ·x.sup.s-2 + . . . +a.sub.o                                                  (12)

The Fire code is encoded by expressing a product D(x)·x^(m+c) such thatit is divisible by a generator polynomial G(x) without a residue. Thepolynomial D(x) represents a bit data (a_(s-1), a_(s-2), . . . a_(o))sent out to the transmission line.

A residue produced when D(x)·x^(m+c) is divided by G(x) is representedby a check pattern R(x)=R_(m+c-1) ·x^(m+c-1) +R_(m+c=2) ·x^(m+c-2) + . .. +R_(o) (a bit length of the check pattern R(x) is m+c). Thus,

    D(x)·x.sup.m+c =G(x)·Q(x)+R(x)

where Q(x) is a quotient.

The code word of the Fire code is represented by

    F(x)=D(x)·x.sup.m+c +R(x)                         (13)

F(x) is divisible by G(x) without a residue and the encoding of the Firecode is terminated.

FIG. 7 shows an encoder FSRG when the generator polynomial G(x) used isrepresented by

    G(x)=(x.sup.11 +x.sup.2 +1)(x.sup.21 +1)=x.sup.32 +x.sup.23 +x.sup.11 +x.sup.2 +1                                               (14)

The FSRG is a divider which divides the transmitted bit data D(x) by thepolynomial represented by the formula (14). Numerals 1-32 in FIG. 7denote stages in shift registers. A total number of stages is equal tothe maximum order. The data in the respective stages are shifted to thenext stages by a clock signal from a line 61. Numerals 40-44 denoteexclusive OR gates (EOR gates).

Such dividers are well known.

In order for the FSRG to be a divider having G(x) as a divisor, an EORgate is provided between each register having the reference numeralwhich is one larger than the order of each term of G(x) (23, 21, 11, 2,0 in the formula (14)) and the preceding stage, and an output terminalof the EOR 40 is connected to another input terminal of each EOR.

When the transmitted data D(x) is sequentially supplied to the FSRG froma_(s) to a_(o), the content in the stages 1-32 is the check patternR(x).

Then, a switch 50 is connected to ground to start shifting the take outR(x) from the stage 32. It is transmitted following the transmission bitdata. In this manner, the code word F(x) of the Fire code is generated.

(2) Method of Decoding the Fire code

A receiving station receives the input code word F*(x)·F*(x) is dividedby the generator polynomial. It must be divisible without a residue ifno error is included in F*(x). (The transmitted code word F(x) of theFire code is divisible by G(x) without a residue.) However, if F*(x)includes a burst error B(x) starting from a (j+1)th bit, F*(x) is notdivisible by G(x). F*(x) under this condition is represented by

    F*(x)=F(x)+x.sup.j ·B(x)                          (15)

The generator polynomial G(x) consists of the irreducible polynomialP(x) and the polynomial (x^(c) +1). Residues produced by dividing F*(x)by those polynomials are syndromes R_(p) (x) and R_(c) (x),respectively. Those syndromes are multiplied by x^(n-j) and the productsare divided by P(x) and (x^(c) +1), respectively. If residues thereofare equal, (j+1) represents the error position and x^(n-j) ·R_(p) (x)represents the burst error B(x). Accordingly, the followingrelationships are met ##EQU14## where x^(j) ·B(x)≡R_(p) (x) (mod P(x))represents that the residues divided by P(x) are equal. FIG. 8 shows adecoder. FSRP denotes a divider which divides the input code word F*(x)supplied via a signal line 160 by the generator polynomial P(x). FSRCdenotes a divider which divides the input code F*(x) by (x^(c) +1). Acoincidence circuit 150 and a zero detector 151 detects the coincidencebetween the contents of the FSRC and the FSRP. When they are coincident,a signal is produced on a signal line 171.

When the input code word F*(x) has been inputted to the FSRC and FSRP,syndromes S_(c) (x) and S_(p) (x) therefor meet the following becausethe input code is inputted to the output stages of respective m-stageshift registers.

    x.sup.j+m ·B(x)=S.sub.p (x) (mod P(x)

    x.sup.j+m ·B(x)=S.sub.c (x) (mod x.sup.c +1)

In order to multiply those by x^(n-j-m) to render them coincident, theshifting is effected in the FSRC and the FSRP (n-j-m) times with zeroinput. ##EQU15##

In this prior art decoding method, a maximum of (n-m) times of shiftingare necessary.

When such a recording method is actually used, a maximum of (n-m) timesof shifting are required whatever low the order of the input code F*(x)is.

For example, in a disk storage for data, one sector has 128 bytes (1024bits) or 256 bytes (2047 bits). On the other hand, in the Fire codewhich uses the generator polynominal G(x) is represented by the formula(14), n=42987 which is approximately 20-40 times as long. Even in thiscase, approximately 40 thousands times of shifting are required.

On the other hand, however small the code length of the input code F*(x)is, the code length n can not be reduced because the code length n ofthe Fire code F(x) is largely related to the correctable burst errorlength. More specifically, when the correctable error length is given, mis determined and c is determined. On the other hand, e is determinedbased on m, and n is determined based on c and e. Accordingly, in orderto increase the correctable error length, n must be increased.

In order to reduce the number of times of shifting, it has been proposedto use the "Chinese Remainder Therorem" (See "Burst-Correcting Code withHigh Speed Decoding" referenced above.) When it is applied to thedecoding of the Fire code, the FSRC is shifted until FSRC_(L) isrendered all-zero, and then the FSRP is shifted until it coincides withFSRC_(H). The error location (j+1) is determined by the number r_(c) oftimes of shifting required for the FSRC, the number r_(p) of times ofshifting required for the FSRP and constant Ac and Ap, in accordancewith the following formula.

    j=Ac·e.sup.rc +Ap·c.sup.rp (mod n)       (19)

However, this method needs a divider having a divisor n to resolve theformula (19), and hence a complex hardware.

In accordance with the present embodiment, the number of times ofshifting is reduced when the length of the input code is small so thatthe Fire code is decoded with a small increase of the hardware.

The decoding method of the present embodiment is now explained.

In describing the present embodiment, let us assume that the input codeF*(x) is represented as follows.

    F*(x)=b.sub.s+m+c-1 ·x.sup.s+m+c-1 +b.sub.s+m+c-2 ·x.sup.s+m+c-2 + . . . +b.sub.O                  (20)

where s is a length of a data field of the input code word and n>>s+m+c,and b_(s-1) -b_(o) are input data bits.

The Fire code F(x) can decode a code having a length of up to n.Accordingly, coefficients of terms x^(n-1) to x^(s+m+c) in the formula(20) are zero.

In order to detect the burst error from the input code word F*(x), atleast (n-s-m-c) times of shifting by the formula (18) are required.Since n>>s+m+c, the number of times of shifting is very large. In orderwords, the error location j cannot be detected before such number oftimes of shifting. If most parts of the huge member of times of shiftingcan be omitted, the object of the present invention can be attained.

In the present invention, the following points were noticed.

(1) The irreducible polynomial P(x) has a period e. It means that if aproduct of a polynomial R_(p) (x) having a lower order than P_(i) (x)and x^(e) is divided by P(x), a residue is equal to the polynomial R_(p)(x). For example, in FIG. 8, the content of the divider FSRP returns tothe original one after e times of shifting.

(2) When the Fire code F(x) is divided into e-bit blocks, the input codeword F*(x) appears in the latter half blocks.

(3) The polynomial (x^(c) +1) also has a period c. For example, thecontents of the dividers FSRC and FSRP of FIG. 8 returns to the originalones after c times of shifting.

(4) The polynomial P(x) and the polynomial (x^(c) +1) have differentperiods from each other. When the polynomials R_(p) (x) and R_(c) (x)are multiplied by x^(e) and the products are divided by P(x) and (x^(c)+1), respectively. The residue produced when divided by P(x) is equal toR_(p) (x) but the residue produced when divided by (x^(c) +1) is

    x.sup.e ·R.sub.c (x)=x.sup.e-βc ·R.sub.c (x) (mod x.sup.c +1)

where β is a maximum integer which meets e≧β_(c).

The value of β can be calculated, then e-βc is determined, and R_(c) (x)is multiplied by x³⁻βc and the product is divided by (x³ +1). This isequivalent to multiplying R_(p) (x) and R_(c) (x) by x^(e) and dividingthe products by P(x) and (x^(c) +1), respectively.

For example, when (e-βc) is determined and the FSRC is shifted (e-βc)times, it is equivalent to shifting the FSRC and the FSRP e times.

(5) The order (s+m+c) of the input code F*(x) is much smaller than thecode length n.

As shown in FIG. 9, at least (n-s-m-c) times of division are requiredbefore the error location is detected. The period e is cycled t timesduring this period. The value of t can be obtained by calculation. Onthe other hand, R_(c) (x) is multiplied by x^(et) and the product isdivided by (x^(c) +1). The residue produced is a quotient of a productof R_(c) (x) and x^(p), divided by (x^(c) +1). Namely, the period c of(x^(c) +1) is cycled k times during (e·t) cycles. A difference betweene·t and c·k is P. The value of P can be determined by calculation.Accordingly, P is first determined, R_(c) (x) is multiplied by x^(p) andthe product is divided by (x^(c) +1). This is equivalent to multiplyingR_(p) (x) and R_(c) (x) by x^(et) and dividing the products by P(x) and(x^(c) +1), respectively.

For example, when the FSRC is shifted P times, it is equivalent toshifting the FSRP and the FSRC e·t times.

(6) Those are sequentially multiplied by x and the products are dividedby P(x) and (x^(c) +1), respectively. The error location is detected bythe number j of multiplication by x when the residues of both divisionsare equal.

The above operations will be represented by formulas.

The syndromes R_(p) (x) and R_(c) (x) are first determined.

    R.sub.p (x)≡F*(x) (mod P(x)

    R.sub.c (x)≡F*(x) (mod x.sup.c +1)

Then, R_(c) (x) is multiplied by x^(p) and the product is divided by(x^(c) +1).

    R.sub.p (x)≡x.sup.e·t ·R.sub.p (x)≡F*(x) (mod P(x)

    x.sup.p R.sub.c (x)≡x.sup.e·t ·R.sub.c (x)≡x.sup.ck+p ·R.sub.c (x) (mod x.sup.c +1)

Finally, those are multiplied by x^(j), respectively.

    B.sub.p ·(x)≡x.sup.j ·R.sub.p (x)≡x.sup.j ·F*(x) (mod P(x)

    B.sub.c (x)≡x.sup.p+i ·R.sub.c (x)≡x.sup.p+i ·F*(x) (mod x.sup.c +1)

The integer j when B_(p) (x) and B_(c) (x) are equal represents theerror location. The B_(p) (x) at this time represents the burst errorB(x) pattern.

In summary, the integer j can be determined from

    B.sub.p (x)=x.sup.j ·F*(x) (mod P(x))

    B.sub.c (x)=x.sup.p+j ·F*(x) (mod x.sup.c +1)

    B.sub.p (x)=B.sub.c (x)=B(x)

The construction of the present embodiment will now be explained withreference to the drawings. Let us assume the Fire code whose generatorpolynomial G(x) is represented by the formula (14). The code length n isgiven by

    n=21×(2.sup.11 -1)=42987                             (21)

The length of the check pattern R(x) is 32 bits. One burst error havinga length of up to b=11 bits is correctable (b≦m).

FIGS. 8 and 10 show a decoder for the Fire code represented by theformula (14) and a control circuit therefore. Stages 501-511 and anexclusive OR gate 540 constitute the divider FSRP having the polynomial(x¹¹ +x² +1) as a divisor. Stages 512-532 constitute the divider(feedback shift register FSRC) having the polynomial (x²¹ +1) as adivisor. The stages 512-522 are called FSRC_(L) and the stages 523-532are called FSRC_(H). A coincidence circuit 550 checks the coincidencebetween the bits of the FSRP and the FSRC_(L), that is, the stages 501and 512, 502 and 513, 503 and 514, 504 and 515, 505 and 516, 506 and517, 507 and 518, 508 and 519, 509 and 520, 510 and 521, and 511 and522. A zero detector 551 checks whether all of the stages 523-532 arezero. An AND gate 570 renders a signal line 571 high level when both thecoincidence circuit 550 and the zero detector 551 are high level. When asignal line 561 changes to high level, the FSRP is shifted, and when asignal line 562 changes to high level, the FSRC (FSRC_(H) and FSRC_(L))is shifted.

The decoding operation will now be explained. The decoding is done bythe following three steps.

5 (S1) Generation of syndromes S_(c) (x) and S_(p) (x)

(S2) Preshifting of FSRC by P times

(S3) Determination of error pattern B(x) and error location j

A circuit shown in FIG. 10 controls the above three steps, and FIGS. 11,12 and 14 show timing charts for the processes in the steps (S1), (S2)and (S3), respectively. The processes in the steps (S1), (S2) and (S3)are now explained.

The step (S1)-generation of syndromes is first explained. In FIG. 8, theinput data 560 is supplied to the FSRP and FSRC through the exclusive ORgates 541 and 542, respectively. A set of contents of the FSRP and FSRCat the end of the inputting of the data is the syndrome for the Firecode.

Shift enable signals 561 and 562 are generated by the circuit of FIG. 10and the timing thereof is shown in the timing chart of FIG. 11.Referring to FIGS. 10 and 11, a signal line 600 from a transmissioncontrol unit 623 for controlling the signal reception is rendered highlevel in synchronism with a clock φ₂ at a timing T₁ one clock before thefirst bit data of the input data 560 (F*(x)) is supplied to the decoder.The signal line 600 renders a Q-output of a flip-flop 602 low level, andthe Q-output is sent to signal lines 561 and 562 through a clock gate603 which receives a clock input φ₂ and OR gates 604 and 605.Accordingly, the signal lines 561 and 562 are rendered high level insynchronism with the first bit data of the input data 560. A signal line601 indicates the end of the input data. It is rendered high level atthe timing T₂ in synchronism with the last big data of the input data560. The signal line 601 renders the Q-output of the flip-flop 602 highlevel and renders the signal lines 561 and 562 low level through theclocked gate 603 and the OR gates 604 and 605. As shown in FIG. 11, whenthe syndromes S_(p) (x) and S_(c) (x) are generated, the signal lines561 and 562 are rendered high level only for the period of data input.The set of contents of the dividers FSRP and FSRC at the end ofinputting of the last bit of the input data are the syndromes S_(p) (x)and S_(c) (x). In FIGS. 10, 11, 12 and 14, φ₁ and φ₂ representnon-overlapping two-phase clocks.

The steps (S2)--preshifting will now be explained. In this step,shifting is effected only in the FSRC by P times. Calculation method forP will be explained later. The preshifting serves to substantiallyreduce the number of times of shifting when the length of the input codeword F*(x) is short, such as the disk data.

A preshift start signal 606 renders the Q-output of the flip-flop 607low level at a timing T_(a) of FIG. 6 and renders the signal lines 562and 610 high level through a clocked gate 608 which receives the clockinput φ₂ and OR gates 605 and 609. The high level on the signal line 562permits the shifting of the FSRC and the high level on the signal line610 permits the incrementing of the counter. The preshift start signal606 is supplied to a clear terminal of the counter 613 through a NORgate 611 and a clocked gate 612 which receives the clock input φ₁. As aresult, an output 614 from the counter 613 is set to "0" in synchronismwith the clock following the preshift start signal 606. A record lengthRL and a calculated number P of times of preshifting are supplied to apreshift count detector 615, which renders the signal line 616 highlevel and resets the flip-flop 607 when the output of the clocked gate608 is high level and the output 614 of the counter 613 is (P-1) (at atiming T_(b)). As shown in FIG. 12, the signal line 662 is rendered highlevel only for the durations of the P clocks so that the shifting iseffected P times in the FSRC.

The number P of times of preshifting will now be explained. In thegenerator polynomial shown by formula (14), the polynomial (x¹¹ +x² +1)is a primitive polynomial and the period e of the FSRP is 2047 (=2¹¹-1). The FSRC represented by the polynomial (x²¹ +1) is a simplerotation and the period thereof is 21. The patterns of the FSRP and FSRCreturn to their original ones after 2047 and 21 times of shiftings,respectively. Accordingly, if the shifting is omitted by a number oftimes equal to a multiple of 2047, no shifting is required for the FSRPand a maximum of 20 times of shifting is required for the FSRC dependingon the number of times of shifting omitted. The number of times ofpreshifting is P.

In the disk data, the record length RL is 128, 256 , . . . bytes. Forthe Fire code whose generator polynomial is shown by the formula (14),the number P of times of preshifting is explained with reference to FIG.9.

Since the sector data has 1024 bits and the length of the check patternR(x) is 32 bits, the leading 41931 bits of the 42987-bit Fire code maybe considered all-zero. Especially, 2047×20=40940 bits of the 41931 bitmay be considered all-zero. In this case, the number P of times ofpreshifting is given by ##EQU16## where a represents a round-up numberof a.

The number of times of shifting omitted is e·t, where ##EQU17##

The number P of times of preshifting in the FSRC is formalized. Assumingthat the record length of the disk data is RL bytes, (RL×8+32)-bit data,including the 32-bit Fire code check pattern, is recorded on the disk.Accordingly, the length of the input code F*(x) is (RL×8+32) and amaximum of {42987-(RL×8+32)} times of shifting can be omitted. If##EQU18## leading bits are considered all-zero, the number P of times ofpreshifting in the FSRC is represented by ##EQU19## FIG. 13 shows anexample of calculation of RL and P.

The final step (S3) will now be explained. This step determines theerror pattern B(x) and the error location j. In FIG. 10, the errordetection start signal 617 renders the Q-output of the flip-flop 618 lowlevel at a timing t₁ (FIG. 6) and renders the signal lines 561, 562 and610 high level through the clocked gate 619 which receives the clockinput φ₂ and the OR gates 604, 605 and 609. At the same time, the errordetection start signal 617 clears the counter 613 through the NOR gate611 and the clocked gate 612. As shown in FIG. 14, the signal lines 561and 562 are rendered high level at the clock φ₂ following the errordetection start signal 617 to start the shiftings in the FSRP and FSRC,and the output 614 of the counter 613 is incremented from "0".

The shiftings in the FSRC and FSRP are effected until any of thefollowing conditions is met.

(C1) The bits of the FSRP and the bits of the FSRC_(L) are coincidentand the bits of the FSRC_(H) are all-zero.

(C2) The number of times of shifting exceeds a predetermined number Q.

When the condition (C1) is met, the signal line 571 in FIG. 8 isasserted, and the error pattern is represented by the bits of the FSRCand the error location is at 40940+number j of times shifting from theleading position. The condition (C2) is detected by a shift overdetector 620 of FIG. 9 by the output of the clocked gate 619 and thecounter output 614. The number Q may be a number larger than (RL×8+32).When it is a multiple of 4098, the detector may be simplified. FIG. 15shows an example of calculation of Q. The condition (C2) indicates theoccurrence of a uncorrectable error.

When the condition (C1) or (C2) is detected, the signal line 622 in FIG.9 is rendered high level through the OR gate 621 and the flip-flop 618is reset at a timing t₂. As shown in FIG. 14, when the error detectionstart signal 617 is rendered high level, the signal lines 561 and 562are rendered high level at the next clock φ₂ and the counter output 614is incremented from "0". When the condition (C1) or (C2) is thereafterdetected, the signal line 622 is rendered high level and the signallines 561 and 562 are negated. The incrementing of the counter isstopped.

The steps (S1), (S2) and (S3) described above are the decoding methodfor the Fire code in the present invention.

Assuming that the Fire code whose generator polynominal is representedby the formula (14) and the record length RL is 128 bytes, the prior artmethod required a maximum of (42987-11) times of shifting while thepresent method requires only (2048+11) times of shifting. Assuming thatone shift cycle requires 100 ns (10 MHz), the prior art method needsapproximately 4.3 seconds while the present method needs only 0.2second. The advantage from a practical point of view is great.

When the "high speed decoding method based on the Chinese RemainderTheorem" is used, the division by an integer n shown by the formula (15)is necessary. In the Fire code which uses the generation polynominalG(x) shown by the formula (14), n=42987 and 17-bit division is required.Accordingly, it is not appropriate for an 8/16-bit microcomputer. Thepresent invention requires no such division.

In the above embodiment, after the P times of preshifting, the FSRP andthe FSRC are shifted until their contents coincide. Alternatively, theFSRC and FSRP may be synchronously shifted q' times before or after theP times of preshifting, where

    q'=(c-p)·e-(s+m+c)

and then they may be synchronously shifted until the contents thereofcoincide.

In the above embodiment, the FSRC is preshifted. Alternatively, the FSRPmay be preshifted. In this case, the number P' of times of preshiftingis given by ##EQU20##

While particular embodiments of the invention has been shown anddescribed, it will be obvious to those skilled in the art that variouschanges and modifications may be made without departing from the presentinvention in its broader aspect.

What is claimed is:
 1. In an apparatus for decoding a cyclic codegenerated by a generator polynomial ##EQU21## (where P_(i) (x) is am_(i) -order irreducible polynomial) including 0-th to l-th feedbackshift registers corresponding to the terms (x^(c) +1) and P_(i) (x), anerror detecting circuit for detecting coincidence of a predeterminednumber of low order bits of said 0-th to l-th feedback shift registersand for detecting an all-zero condition of the high order bits of said0-th to l-th feedback shift registers, said predetermined number being aminimum one of the numbers of bits (c, m₁, m₂, . . . m_(l)) of saidfeedback shift registers, said 0-th feedback shift register having anoutput terminal thereof connected to an input terminal thereof, and said1st to l-th feedback shift registers each having an output terminalthereof connected to an input terminal thereof and having exclusive ORgates inserted between stages determined by the associated irreduciblepolynomial, said exclusive OR gates each receiving the output of theassociated feedback shift register as one input thereto and said 0-th tol-th feedback shift registers having data input terminals at the b-thstage, where b is the minimum numbers of bits (c, m₁, m₂, . . . m_(l))of said feedback shift registers;a method for decoding said cyclic codefor correcting a single burst error by shifting said 0-th to l-thfeedback shift registers until said error detecting circuit detects thecoincidence and all-zero condition, comprising the steps of: shifting atleast one of said 0-th to l-th feedback shift registers a predeterminednumber of times; and after said predetermined number of shifting,shifting said 0-th to l-th feedback shift registers simultaneously untilsaid error detecting circuit detects the coincidence and all zerocondition.
 2. An apparatus for decoding a cyclic code generated by agenerator polynomial ##EQU22## (where P_(i) (x) is a m_(i) -orderirreducible polynomial) comprising: -th to l-th feedback shift registerscorresponding to the terms (x^(c) +1) and P_(i) (x), said 0-th feedbackshift register having an output terminal thereof connected to an inputterminal thereof, and said 1st to l-th feedback shift registers eachhaving an output terminal thereof connected to an input terminal thereofand having exclusive OR gates inserted between stages determined by theassociated irreducible polynomial, said exclusive OR gates eachreceiving the output of the associated feedback shift register as oneinput thereto and said 0-th to l-th feedback shift registers having datainput terminals at the b-th stage, where b is the minimum numbers ofbits (c, m₁, m₂, . . . m_(l)) of said feedback shift registers;an errordetecting circuit for detecting coincidence of a predetermined number oflow order bits of said 0-th to l-th feedback shift registers and fordetecting an all-zero condition of the high order bits of said 0-th tol-th feedback shift registers, said predetermined number being a minimumone of the numbers of bits (c, m₁, m₂, . . . m_(l)) of said feedbackregisters; a first controller for shifting at least one of said 0-th tol-th feedback shift registers a predetermined number of times; and asecond controller for shifting said 0-th to l-th feedback shiftregisters simultaneously after said predetermined number of times ofshifting by said first controller until said error detecting circuitdetects the coincidence and all-zero condition.
 3. An apparatus fordecoding a Fire code comprising:first and second feedback shiftregisters for receiving an input code, said first feedback shiftregister having an output terminal thereof connected to an inputterminal thereof and having an exclusive OR gate inserted between stagesthereof, said second feedback shift register having an output terminalthereof connected to an input terminal thereof and having an exclusiveOR gate inserted between stages thereof, said exclusive OR gatereceiving the output of said second feedback shift register as one inputthereto; an error detecting circuit for detecting coincidence of thelower c bits of said first and second feedback shift registers and fordetecting an all-zero condition of the high (c-m) bits of said secondfeedback shift register; a first controller for shifting one of saidfirst and second feedback shift registers a predetermined number oftimes; and a second controller for shifting said first and secondfeedback shift registers simultaneously after the shifting by said firstcontroller until said error detecting circuit detects the coincidenceand all-zero condition, whereby a burst error is detected.
 4. A methodfor decoding a Fire code generated by a generator polynomialG(x)=P(x)·(x^(c) +1), where P(x) is an m-order irreducible polynomials,and received as a received code F*(x), and for correcting a single bursterror, with an apparatus including a first feedback shift register, anda second feedback shift register, said first feedback shift registerhaving an output terminal thereof connected to an input terminal thereofand having an exclusive OR gate inserted between the stages thereof,said exclusive OR gate receiving the output of said feedback shiftregister as one input thereto, said second feedback shift registerhaving an output terminal thereof connected to an input terminalthereof, and an error detecting circuit for detecting coincidence of thelower c bits of said first and second feedback shift registers and fordetecting all-zero condition of high (c-m) bits of said second feedbackshift registers, said method comprising the steps of:inputting thereceived code F*(x) in said first feedback shift register, whereby aresidue obtained by dividing F*(x) by P(x) is retained in said firstfeedback shift register when the code F*(x) has been inputted therein,and inputting the received code F*(x) in said second feedback shiftregister, whereby a residue obtained by dividing F*(x) by (x^(c) +1) isremained in said second feedback shift register when the code F*(x) hasbeen inputted therein; shifting said first feedback shift register by γtimes and shifting said second feedback register by ω times,respectively, whereγ and ω are integers

    ω-γ=e·t-c·k

    e·t≦e·c- g

    c·k≦e·c-g

    t=0, 1, . . . , c

    k=0, 1, . . . , e

t and k are not simultaneously zero e is the period of P(x) g is thelength of the input code F*(x); and shifting said first and secondfeedback shift registers simultaneously until said error detectingcircuit detects the coincidence and all-zero conditions, wherein thenumber of times of shifting j shows an error location information.
 5. Amethod for decoding a Fire code according to claim 4 wherein ##EQU23##6. A method for decoding a Fire code according to claim 4 wherein##EQU24##
 7. A method for decoding a Fire code according to claim 4,further comprising the steps of:(a) generating residue polynomials R_(p)(x) and R_(c) (x) by multiplying residues produced when an input codeF*(x) to be decoded is divided by P(x) and (x^(c) +1), respectively, bymultiplier x^(j) ; and (b) selecting an integer j which renders thepolynomials R_(p) (x) and R_(c) (x) equal, as error locationinformation:

    R.sub.p (x)=x.sup.γ+j ·F*(x)(mod P(x))

    R.sub.c (x)=x.sup.ω+j ·F*(x)(mod x.sup.c+1).